1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method of the same.
2. Description of the Related Art
A flash memory having a NAND, AND, or NOR cell array structure is conventionally known as a nonvolatile semiconductor memory device which uses a MOS transistor having a floating gate electrode and control gate electrode as a memory cell. The conventional techniques will be explained below by taking a NAND flash memory as an example.
FIG. 1 is a sectional view showing a portion of the cell array structure of a NAND flash memory.
In a silicon substrate 11, element isolation insulating layers 16 having an STI (Shallow Trench Isolation) structure are formed. Each element isolation insulating layer 16 protrudes from the upper surface of the silicon substrate 11, thereby forming a projection. The upper surface of this element isolation insulating layer 16 is flat.
In each recess formed by the projections of the element isolation insulating layers 16, i.e., on the silicon substrate 11 between these element isolation insulating layers 16, a tunnel oxide film 12 and floating gate electrode (lower portion) 13a are formed. The upper surfaces of the element isolation insulating layers 16 are substantially leveled with the upper surfaces of the floating gate electrodes 13a. 
On each floating gate electrode 13a, a floating gate electrode (upper portion) 13b is formed. The end portions of this floating gate electrode 13b are present on the element isolation insulating layers 16. The floating gate electrodes 13a and 13b have a so-called gull wing shape as a whole.
The upper and side surfaces of each floating gate 13b are covered with an insulating layer 17. This insulating layer 17 has, e.g., an ONO structure. A control gate electrode 18 is formed on the insulating layer 17. This control gate electrode 18 is shared by memory cells arranged in the direction in which the control gate electrode 18 runs.
In this cell array structure, the space between the floating gate electrodes 13b is called a slit structure. This slit structure electrically disconnects the floating gate electrodes 13b adjacent in the direction in which the control gate electrode 18 runs, and also increases the area of a portion where the floating gate electrodes 13a and 13b oppose the control gate electrode 18.
That is, since the upper and side surfaces of the floating gate electrode 13b are covered with the insulating layer 17, the capacitance between the floating gate electrodes 13a and 13b and the control gate electrode 18 can be increased. Accordingly, electric charge can be stored in the floating gate electrodes 13a and 13b for long time periods.
Electrons are injected into the floating gate electrodes 13a and 13b by, e.g., applying a high write potential Vpgm to the control gate electrode 18 and a ground potential Vgnd to the silicon substrate 11. In this case, the electrons move from the silicon substrate 11 to the floating gate electrodes 13a and 13b by the FN tunneling phenomenon.
FIG. 2 shows an equivalent circuit of the memory cell by letting Cip denote the capacitance between the control gate electrode and floating gate electrode, and Ctox the capacitance between the floating gate electrode and silicon substrate.
For example, in the device structure shown in FIG. 1, the control gate electrode 18, insulating layer 17, and floating gate electrodes 13a and 13b can be regarded as capacitors, and the floating gate electrodes 13a and 13b, tunnel oxide film 12, and silicon substrate 11 can also be regarded as capacitors.
That is, as shown in FIG. 2, this memory cell is equivalent to a structure in which the two capacitors Cip and Ctox are connected in series between a control gate electrode CG and silicon substrate.
A potential Vfg of the floating gate electrode when a write potential Vcg (=Vpgm) is applied to the control gate electrode is determined by capacitive coupling between Cip and Ctox, and represented byVfg=Cr×(Vcg−Vt+Vt0)Cr=Cip/(Cip+Ctox)where Vt is the present cell transistor threshold value, and Vt0 is the threshold value (neutral threshold value) when no electric charge is stored in the floating gate electrode.
As Vfg rises, an electric field acting on the tunnel oxide film increases, and this facilitates injection of electric charge into the floating gate electrode.
In addition, according to the above equations, when Vcg is constant, Vfg increases in proportion to a capacitance ratio Cr. That is, when this capacitance ratio Cr is large, Vfg large enough to move electric charge can be obtained even if the write potential Vcg is decreased. As a consequence, the write potential can be reduced.
To increase the capacitance ratio Cr, Cip need only be made as large as possible with respect to Ctox.
The capacitance of a capacitor is proportional to a dielectric constant ∈ of a thin film between opposing electrodes and an area S of the opposing electrodes, and inversely proportional to a distance d between the opposing electrodes.
For example, in the device structure shown in FIG. 1, the gate insulating layer 17 formed between the floating gate electrodes 13a and 13b and control gate electrode 18 is required to have a high dielectric constant, to be thin, and to be in contact with the two gate electrodes 13a and 13b in a broad range.
The tunnel oxide film 12 is very thin because it is formed to allow a tunnel current to easily flow with respect to a high electric field. However, the gate insulating layer 17 is much thicker than this tunnel oxide film 12 in order to prevent a leak by the tunnel current.
That is, to increase the capacitance ratio Cr, it is necessary to increase the dielectric constant of the gate insulating layer 17 and increase the area of a portion where this gate insulating layer 17 comes in contact with the floating gates 13a and 13b and control gate 18, thereby increasing Cip.
As the structure of the gate insulating layer 17 with which Cip is increased, a so-called ONO structure is conventionally known which realizes a dielectric constant larger than that of the material (e.g., SiO2) forming the tunnel oxide film 12. In this ONO structure, SiN is sandwiched between SiO2.
As the structure which increases the area of a portion where the floating gate electrodes 13a and 13b oppose the control gate electrode 18, a technique is known by which the gate insulating layer 17 is formed not only on the upper surfaces but also on the side surfaces of the floating gate electrodes 13a and 13b. 
As micropatterning progresses, however, a reduction in the write potential Vcg has become a very serious problem for downsizing of a driving circuit. This is so because, as described above, Cip must be increased in order to reduce the write potential Vcg. The simplest method of increasing Cip is to increase the thickness of the floating gate electrodes 13a and 13b, thereby increasing the side wall area of these floating gate electrodes 13a and 13b. 
Unfortunately, if the thickness of the floating gate electrodes 13a and 13b is increased, the depth of the slit structure also increases, and this increases the thickness of a mask layer required in slit fabrication. Also, when the floating gate electrodes 13a and 13b are processed, residues of these floating gate electrodes 13a and 13b are produced in the space between the element isolation insulating layers (STI) 16.
Cip can also be increased by using a material having a dielectric constant higher than that of the ONO film. Unfortunately, such a material having a high dielectric constant often has poor coverage for an underlayer having a step. Especially in the example shown in FIG. 1, film quality deterioration in the corners (slit portions) of the floating gate electrodes 13b occurs as a serious problem.
In addition, the etching selectivity of selective etching of a high-dielectric-constant material cannot be well increased compared to those of other materials forming a cell array structure. This makes gate fabrication and the like difficult.
As described above, as memory cell micropatterning advances, the conventional cell array structure cannot increase the capacitance between the floating gate electrodes and control gate electrode without posing any problems in terms of manufacture and the like. This makes it impossible to achieve high integration and a low write potential at the same time.